A framework for the timing analysis of dynamic branch predictors

Real-time systems require predictable processor behavior such that tight upper bounds on the worst-case execution times (WCETs) of their critical tasks can be derived. Methods for estimating these upper bounds received much attention in the last fifteen years. However, the use of high-performance processors to meet ever growing performance requirements demands the development of more and more complex models. This is also the case for dynamic branch prediction schemes that are implemented in processors used in embedded systems. In this paper we focus on the static timing analysis of dynamic branch prediction based on the implicit path enumeration technique. The goal of this paper is to introduce a framework that allow to generate the IPET model of dynamic branch prediction mechanisms. With this framework we generated the models of some branch predictors and compare them.